The present invention relates to systems for, and methods of, recovering digitally modulated television signals and, more particularly, to a dual mode QAM/VSB receiver system for recovering quadrature amplitude modulated or vestigial sideband modulated signals.
Modern digital telecommunication systems are operating at ever-increasing data rates to accommodate society""s growing demands for information exchange. However, increasing the data rates, while at the same time accommodating the fixed bandwidths allocated by the Federal Communications Commission (FCC), requires increasingly sophisticated signal processing techniques. Since low cost, small size and low power consumption are portent in the hardware implementations of such communication systems, custom integrated circuit solutions are important to achieving these goals.
Next generation digital television systems, such as cable transported television (CATV) and high-definition television (HDTV) rely on telecommunication transceivers to deliver data at rates in excess of 30 megabits per second (30 Mb/s). The ATSC A/53 Digital Television Standard, was developed by the xe2x80x9cDigital HDTV Alliancexe2x80x9d of U.S. television vendors, and has been accepted as the standard for terrestrial transmission of SDTV and HDTV signals in the United States. The ATSC A/53 standard is based on an 8-level vestigal sideband (8-VSB) modulation format with a nominal payload data rate of 19.4 Mbps in a 6 MHz channel. A high data rate mode, for use in a cable television environment, is also specified by the standard. This particular mode, defined in Annex D to the ITU-T J.83 specification, utilizes a 16-VSB modulation format to provide a data rate of 38.8 Mbps in a 6 MHz channel.
Transmission modes defined in ITU-T J.83 Annex A/C are used primarily outside the United States for digital cable television transmission. The transmission modes supported by this specification have been adopted in Europe as the Digital Video Broadcast for Cable (DVB-C) standard, and further adopted by the Digital Audio-Video Council (DAVIC) with extensions to support 256-QAM modulation formats.
Beyond these divergent requirements, the ITU-T J.83 Annex B standards define the dominant methodology for digital television delivery over CATV networks in the United States. It has been adopted as the physical layer standard by various organizations including the SCTE DVS-031, MCNS-DOCSIS and the IEEE 802.14 committee.
Given the implementation of multiple modulation techniques in the various adopted standards, there exists a need for a television receiver system capable of receiving and demodulating television signal information content that has been modulated and transmitted in accordance with a variety of modulation formats. In particular, such a system should be able to accommodate receipt and demodulation of at least 8 and 16-VSB modulated signals in order to support US HDTV applications, as well as 64 and 256-QAM modulated signals, for European and potential US CATV implementations.
The present invention is directed to digital data communication systems and methods for operating such systems in order to synchronize a receiver""s time base to a remote transmitters. Carrier frequency and symbol timing information is recovered from a pilot (unsuppressed carrier) signal that is inserted into a VSB spectrum. Carrier frequency and symbol timing information are derived from the augmented piolet signal and are used for spectrum centering and symbol extraction.
Carrier phase tracking is decision directed and is performed by circuitry which is incorporated into a receiver""s adaptive equalizer section. Carrier phase tracking is performed on symbols modulated in accordance with both QAM and VAB modulation schemes, and particularly in the case where VSB signals are treated as OQAM. Treating a VSB signal as OQAM allows for carrier phase tracking systems to evaluate both a symbol""s error magnitude characteristic, but also to evaluate a symbol""s rotational state, in order to define a complete phase error vector for a VSB (OQAM) signal.
In the first aspect of the invention, an integrated circuit digital communication system includes a decision directed symbol error magnitude determination circuit and a symbol rotation direction indication circuit. The symbol error magnitude circuit is operative in response to a first-phase portion of a complex signal, while the symbol rotation direction indication circuit is operative in response to a second-phase portion of the complex signal, offset from the first-phase portion. The decision directed of symbol error magnitude circuit includes a decision circuit operating on the first-phase signal and outputting first-phase decisions. An error circuit sums the first-phase decisions with the first-phase signal in order to define first-phase error term. The symbol rotation direction indication circuit includes a multiplier which combines the first-phase error term with a signal representing a second-phase midpoint signal.
In a further aspect of the invention, an integrated circuit digital communication system includes a decision directed carrier phase recovery circuit for complex signals representing symbols, characterized by in-phase and quadrature-phase portions separated, in time, by an offset. The carrier phase recovery circuit includes a sampling circuit of which samples each of the in-phase and quadrature-phase portions of the complex signal at the in-phase and quadrature-phase sampling times. The signal on each rail is thus sampled twice, once at its symbol sampling time and once at its symbol midpoint time.
A separation circuit separates the sampled in-phase (I) signal into a (I) sample time data stream and an in-phase time offset (XI) data stream, with (XI) being the I midpoint. When both I and Q signals are present, as in the OQAM case, the Q signals are separated into a Q sample time data stream and a XQ offset data stream, with XQ representing the Q midpoint. The XQ and I signals therefore have the same time stamp, as do the XI and Q signals. A decision circuit receives the I data stream and generates a tentative symbolic decision from 1 sample data. The summing circuit combines the symbolic I decisions with signals from the I data stream in order to generate a I symbolic error term (EI). A multiplier combines the EI error term with either XQ, or the sign of XQ in order to define a phase error term PI representing both the error magnitude and rotation direction of symbols on the I rail. Magnitude and direction are, thus, determined from complex signal representations having the same time stamp.
In a further aspect of the invention, the integrated circuit digital communication stream includes a second separation circuit connected to separate sampled Q signals into a Q sample time data stream and a XQ time offset data stream. A second decision circuit receives the Q sample time data stream and generates a tentative Q symbolic decision from Q sample data. The second summing circuit combines the tentative Q symbolic decisions with signals from the Q sample time data stream in order to generate a Q symbolic error term (EQ). The second multiplier circuit combines EQ with XI in order to define a phase error term PQ for signals on the Q rail. PI and PQ signals are sequentially provided by a multiplexer to a loop filter and then to a reference synthesizer circuit which provides phase correction signals to a de-rotator, an operative response to the phase error terms.
In yet a further aspect of the invention, where no signals are present on the Q rail, the system receives I signals and takes their Hilbert transform in a Hilbert transform circuit, in order to internally generate a XQ signal. A decision circuit makes a tentative symbolic decision on I and a summing circuit combines the tentative decision with I in order to generate an error term EI. The error term EI is combined with the Hilbert transform of I, i.e., XQ, in order to define a phase error term PI of which is, in term, directed to a loop filter and reference synthesizer circuit for providing phase correction signals to a de-rotator. The error term EI is directed through a delay matching circuit, constructed to provide an identical delay to the EI term as the Hilbert transform circuit provides on its signal path. Accordingly, EI and XQ signals arrive substantially simultaneously at a multiplier for combination into a PI phase error term.